For some central processing unit (CPU) arrangements such as a dual-thread core processor, multiple threads of execution operate independently to access the same memory array. However, when the multiple threads attempt to access the same wordline of the shared memory array at the same time, a wordline collision occurs. This can result in incorrect data at the output of the memory array or the destruction of content, such as data or instructions, within the memory array.
In the prior art, base and offset operand addition can be used to address content within caches as well as data or instructions within other CPU memory units. Because an addition is performed to arrive at the effective address to access a wordline within the memory array storing the content, some dual-thread traditional processors take at least two clock cycles to access the memory array. A first clock cycle is used to add the base and offset operands for both threads and at least a second clock cycle is used to perform collision detection and access the memory array based on the results of the addition.
The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like reference numbers indicate similar elements. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present disclosure.
The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Also, the functions included in the flow diagrams do not imply a required order of performing the functionality contained therein.